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I am working on a team that is doing both driver software and FPGA development. The FPGA simulation is being done in Modelsim and driver software is written in C. To minimize integration risk, I would love to be able to model the interaction between the two halves of our product before putting it on hardware. I know Modelsim supports a testbench which lets you provide stimulus in the form of a text file with times and values to input.

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I'm wondering if Modelsim has a mode which allows you to hook up a pipe to an external application (such as our driver), and run a sort of distributed simulation where the software can push values into the testbench, then observe the results later. The trick that I cannot do with a text file input is have the two halves of the product interact. I need to have the software 'write' values into the FPGA simulator, read the results, and then write new values into the FPGA which are dependent on the results it read. Text files require the inputs to be independent from the output. I've done searches on both StackExchange and google, but I have not been able to come up with a set of keywords to narrow my search enough to either identify the behavior I am looking for, or determine that it does not exist. Abstract: In this thesis, we present a method of controlling a ModelSim simulation via an external program. Communication between ModelSim and the external program is accomplished by using Named Pipes ('FIFOs'), which appear as normal files to each application.

The main difference between using FIFOs versus normal files for Inter-Process Communication (IPC) is that an application attempting to write to a FIFO is paused until another application attempts to read from the FIFO and vice-versa. This improves reliability of the IPC. You might want to look at. It's a Python based co-simulation library, one of the design goals was to enable the methodology you describe, easily simulating un-modified production software and RTL.

There's an example in the repository of running unmodified ping command against a simulation and a walking through the code. For user-space drivers, configuration utilities etc. You have a couple of options to run your software un-modified: • If your accesses to the device boil down to a few functions (e.g. A read and a write call) you can link against a simulation library which block while performing the access against the simulation.

This works very well for configuration. • If your software uses memory mapped IO and dereferences pointers to access the device then things get slightly more complex - you have to create a shared memory area with protection bits set.

If you use networking then virtual interfaces like TUN/TAP can be used (see the mentioned above), I suspect there may be similar options for USB transfer or other common host interfaces. Cocotb works with a variety of simulators and VHDL (via VHPI) or Verilog/SystemVerilog designs (via VPI). Unfortunately Modelsim doesn't implement VHPI so as a VHDL user you're stuck with FLI, which is not nearly so useful as an interface. You could to try and persuade them to implement an industry standard interface, or you could evaluate another simulator that supports VHPI. Sadly, it appears that tool vendors in general aren't particularly interested in the VHDL market, judging by the time it takes them to implement any VHDL related functionality. Disclaimer: I'm a Cocotb developer.

QuestaSim is a software application developed by Mentor Graphic for testing, scheduling, and debugging of FPGA and SoC chips. It supports a variety of hardware description languages, such as Verilog, SystemVerilog, VHDL, SystemC, PSL, and UPF, and with the various tools it gives you the ability to test the scheduling of the above chips before you actually design and implement it. The Questa Simulator is actually the core of the simulation and debugging of the Questa comprehensive evaluation platform, which reduces the risk of evaluating the chips. Questa covers a large number of abstract layers (TLM, Transaction Level Modeling, RTL, Gates, Transistors, etc.) for designing and evaluating Soc and FPGA chips. It also includes Proof-based Evaluation (ABV), Open-End Evaluation Method (OVM) and a comprehensive evaluation method (UVM) to increase the efficiency of quizzes, automation and reusability. QuestaSim Features and Features: High efficiency and multi-language support for hardware descriptions Efficient and advanced evaluations Easy to use and fast debugging Auto-test production Multi-core simulations and tests in parallel And.